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? semiconductor components industries, llc, 2015 september, 2015 ? rev. 5 1 publication order number: kai ? 16000/d kai-16000 4872 (h) x 3248 (v) interline ccd image sensor descriptio n the kai ? 16000 is an interline transfer ccd offering 16 million pixels at up to 3 frames per second through 2 outputs. this image sensor is organized into an array of 4,872 (h) x 3,248 (v) with 7.4 micron square pixels and full 35 mm optical format. as an interline transfer ccd, the kai ? 16000 includes additional features such as progressive scan readout, electronic shutter, low noise, high dynamic range, and blooming suppression. these features make the kai ? 16000 the perfect sensor for applications in industrial, aerial, security, and scientific markets. table 1. general specifications parameter typical value architecture interline ccd; progressive scan total number of pixels 4960 (h) x 3324 (v) = 16.6m number of effective pixels 4904 (h) x 3280 (v) = 16.1m number of active pixels 4872 (h) x 3248 (v) = 15.8m pixel size 7.4 m (h) x 7.4 m (v) active image size 36.1 mm (h) x 24.0 mm (v) 43.3 mm (diagonal), 35 mm optical format aspect ratio 3:2 number of outputs 1 or 2 saturation signal 30,000 electrons output sensitivity 30 v/e ? quantum efficiency kai ? 16000 ? axa kai ? 16000 ? cxa (rgb) kai ? 16000 ? fxa (rgb) 47% 29%, 38%, 44% 31%, 39%, 45% read noise (f = 30 mhz) 16 electrons dark current < 0.5 na/cm 2 dark current doubling temperature 7 c dynamic range 65 db charge transfer efficiency 0.99999 blooming suppression > 100 x smear < ? 80 db image lag < 10 electrons maximum data rate 30 mhz per channel package 40 pin grid array cover glass ar coated, 2 sides note: all parameters above are specified at t = 40 c www.onsemi.com figure 1. kai ? 16000 ccd image sensor features ? 16 million pixel resolution ? electronic shutter ? 35 mm optical format ? progressive scan readout ? high sensitivity ? fast frame rate ? > 60 db dynamic range applications ? industrial ? aerial photography ? security ? scientific see detailed ordering and shipping information on page 2 of this data sheet. ordering information
kai ? 16000 www.onsemi.com 2 ordering information table 2. ordering information part number description marking code kai ? 16000 ? aaa ? jr ? b1 monochrome, no microlens, pga package, taped clear cover glass with ar coating (2 sides), grade 1 kai ? 16000 ? aaa serial number kai ? 16000 ? aaa ? jr ? b2 monochrome, no microlens, pga package, taped clear cover glass with ar coating (2 sides), grade 2 kai ? 16000 ? aaa ? jr ? ae monochrome, no microlens, pga package, taped clear cover glass with ar coating (2 sides), engineering grade kai ? 16000 ? aaa ? jd ? b1 monochrome, no microlens, pga package, sealed clear cover glass with ar coating (2 sides), grade 1 kai ? 16000 ? aaa ? jd ? b2 monochrome, no microlens, pga package, sealed clear cover glass with ar coating (2 sides), grade 2 kai ? 16000 ? aaa ? jd ? ae monochrome, no microlens, pga package, sealed clear cover glass with ar coating (2 sides), engineering grade kai ? 16000 ? axa ? jd ? bx monochrome, special microlens, pga package, clear cover glass with ar coating (both sides), special grade kai ? 16000 ? axa serial number kai ? 16000 ? axa ? jd ? b1 monochrome, special microlens, pga package, clear cover glass with ar coating (both sides), grade 1 kai ? 16000 ? axa ? jd ? b2 monochrome, special microlens, pga package, clear cover glass with ar coating (both sides), grade 2 kai ? 16000 ? axa ? jd ? ae monochrome, special microlens, pga package, clear cover glass with ar coating (both sides), engineering grade kai ? 16000 ? axa ? jr ? b1 monochrome, special microlens, pga package, taped clear cover glass with ar coating (2 sides), grade 1 kai ? 16000 ? axa ? jr ? b2 monochrome, special microlens, pga package, taped clear cover glass with ar coating (2 sides), grade 2 kai ? 16000 ? axa ? jr ? ae monochrome, special microlens, pga package, taped clear cover glass with ar coating (2 sides), engineering grade kai ? 16000 ? fxa ? jd ? b1 gen2 color (bayer rgb), special microlens, pga package, clear cover glass with ar coating (both sides), grade 1 kai ? 16000 ? fxa serial number kai ? 16000 ? fxa ? jd ? b2 gen2 color (bayer rgb), special microlens, pga package, clear cover glass with ar coating (both sides), grade 2 kai ? 16000 ? fxa ? jd ? ae gen2 color (bayer rgb), special microlens, pga package, clear cover glass with ar coating (both sides), engineering grade kai ? 16000 ? cxa ? jd ? b1 (note 1) gen1 color (bayer rgb), special microlens, pga package, clear cover glass with ar coating (both sides), grade 1 kai ? 16000 ? cxa serial number kai ? 16000 ? cxa ? jd ? b2 (note 1) gen1 color (bayer rgb), special microlens, pga package, clear cover glass with ar coating (both sides), grade 2 kai ? 16000 ? cxa ? jd ? ae (note 1) gen1 color (bayer rgb), special microlens, pga package, clear cover glass with ar coating (both sides), engineering grade 1. not recommended for new designs. see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com.
kai ? 16000 www.onsemi.com 3 device description architecture figure 2. sensor architecture 4872 (h) x 3248 (v) active pixels g g r b g g r b g g r b g g r b pixel 1,1 16 buffer rows 16 buffer rows 40 gray rows 16 buffer columns 16 buffer columns 28 black columns 28 black columns 12 dummy pixels 12 dummy pixels dual output or video l video r 12 28 16 4872 16 28 single 12 28 16 2436 2436 16 28 12 fast line dump left ? 2480 4 gray rows fast line dump right ? 2480 there are 40 light shielded gray rows followed 3280 photoactive rows and finally 4 more light shielded gray rows. the first 16 and the last 16 photoactive rows are buffer rows giving a total of 3248 lines of image data. in the single output mode all pixels are clocked out of the video l output in the lower left corner of the sensor. the first 12 empty pixels of each line do not receive charge from the vertical shift register. the next 28 pixels receive charge from the left light shielded edge followed by 4904 photosensitive pixels and finally 28 more light shielded pixels from the right edge of the sensor. the first 16 and last 16 photosensitive pixels are buffer pixels giving a total of 4872 pixels of image data. in the dual output mode the clocking of the right half of the horizontal ccd is reversed. the left half of the image is clocked out v ideo l and the right half of the image is clocked out video r. for the video l each row consists of 12 empty pixels followed by 28 light shielded pixels followed by 2452 photosensitive pixels. for the video r each row consists of 12 empty pixels followed by 28 light shielded pixels followed by 2452 photosensitive pixels. when reconstructing the image, data from video r will have to be reversed in a line buffer and appended to the video l data. the gray rows are not entirely dark and so should not be used for a dark reference level. use the dark columns on the left or right side of the image sensor as a dark reference. of the dark columns, the first and last dark columns should not be used for determining the zero signal level. some light does leak into the first and last dark columns.
kai ? 16000 www.onsemi.com 4 physical description pin description and device orientation figure 3. package pin designations ? top view pixel 1,1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 table 3. pinout pin name description 1 voutl video output, left 2 vddl v dd , left 3 gnd ground 4 resetl reset gate, left 5 hlastl horizontal clock, last stage, left 6 h2bl horizontal clock, phase 2, barrier, left 7 h1bl horizontal clock, phase 1, barrier, left 8 h1sl horizontal clock, phase 1, storage, left 9 h2sl horizontal clock, phase 2, storage, left 10 esd esd protection disable 11 gnd ground 12 h2sr horizontal clock, phase 2, storage, right 13 h1sr horizontal clock, phase 1, storage, right 14 h1br horizontal clock, phase 1, barrier, right 15 h2br horizontal clock, phase 2, barrier, right 16 hlastr horizontal clock, last stage, right 17 resetr reset gate, right 18 gnd ground 19 vddr v dd , right 20 voutr video output, right pin name description 40 fdgl fast line dump gate, left 39 rdl reset drain, left 38 sub substrate 37 gnd ground 36 v1 vccd gate 1, phase 2 35 v5 vccd gate 5, phase 2 34 v9 vccd gate 9, phase 2 33 v3 vccd gate 3, phase 2 32 v7 vccd gate 7, phase 2 31 v11 vccd gate 11, phase 2 30 v2 vccd gate 2, phase 1 29 v6 vccd gate 6, phase 1 28 v10 vccd gate 10, phase 1 27 v4 vccd gate 4, phase 1 26 v8 vccd gate 8, phase 1 25 v12 vccd gate 12, phase 1 24 gnd ground 23 sub substrate 22 rdr reset drain, right 21 fdgr fast line dump gate, right
kai ? 16000 www.onsemi.com 5 imaging performance table 4. typical operation conditions unless otherwise noted, the imaging performance specifications are measured using the following conditions. description condition notes frame time 908 msec 1 horizontal clock frequency 20 mhz light source continuous red, green and blue illumination centered at 450, 530 and 650 nm 2, 3 operation nominal operating voltages and timing 1. electronic shutter is not used. integration time equals frame time. 2. leds used: blue: nichia nlpb500, green: nichia nspg500s and red: hp hlmp ? 8115. 3. for monochrome sensor, only green led used. table 5. specifications description symbol min. nom. max. units sample plan 7 temperature tested at ( c) notes global non ? uniformity n/a 2.5 5.0 %rms die 27, 40 1 maximum photoresponse nonlinearity nl n/a 2 % design 2, 3 maximum gain difference between outputs g n/a 10 % design 2, 3 maximum signal error due to nonlinearity differences nl n/a 1 % design 2, 3 horizontal ccd charge capacity hne 100 ke ? design vertical ccd charge capacity vne 50 ke ? die 27, 40 photodiode charge capacity pne 28 30 ke ? die 27, 40 4 horizontal ccd charge transfer efficiency hcte 0.99999 n/a design vertical ccd charge transfer efficiency vcte 0.99999 design photodiode dark current ipd n/a n/a 40 0.01 350 0.1 e/p/s na/cm 2 die 40 vertical ccd dark current ivd n/a n/a 400 0.12 1711 0.5 e/p/s na/cm 2 die 40 dark current doubling temperature t n/a 7 n/a c design image lag lag n/a <10 50 e ? design antiblooming factor xab 100 300 n/a design vertical smear smr n/a ? 80 ? 75 db design read noise n e ? t 16 e ? rms design 5 dynamic range dr 65 db design 5, 6 output amplifier dc offset v odc 4 9.5 14 v die 27, 40 output amplifier bandwidth f ? 3db 140 mhz design output amplifier impedance r out 100 130 200 die 27, 40 output amplifier sensitivity v/ n 30 v/e ? design 1. per color 2. value is over the range of 10% to 90% of photodiode saturation. 3. value is for the sensor operated without binning. 4. the operating value of the substrate voltage, vab, will be marked on the shipping container for each device. the value of vab is set such that the photodiode charge capacity is 30,000 electrons. 5. at 30 mhz 6. uses 20log (pne/ n e ? t ) 7. ?die? indicates a parameter that is measured on every sensor during the production testing. ?design? designates a parameter that is q uantified during the design verification activity.
kai ? 16000 www.onsemi.com 6 table 6. kai ? 16000 ? aaa description symbol min. nom. max. units sample plan 1 temperature tested at ( c) notes peak quantum efficiency qe max 11 n/a % design peak quantum efficiency wavelength qe n/a 500 n/a nm design 1. ?die? indicates a parameter that is measured on every sensor during the production testing. ?design? designates a parameter that is q uantified during the design verification activity. table 7. kai ? 16000 ? axa description symbol min. nom. max. units sample plan 1 temperature tested at ( c) notes peak quantum efficiency qe max 45 n/a % design peak quantum efficiency wavelength qe n/a 500 n/a nm design 1. ?die? indicates a parameter that is measured on every sensor during the production testing. ?design? designates a parameter that is q uantified during the design verification activity. table 8. kai ? 16000 ? fxa (gen2) description symbol min. nom. max. units sample plan 1 temperature tested at ( c) notes peak quantum efficiency blue green red qe max 45 39 31 n/a n/a n/a % design peak quantum efficiency wavelength blue green red qe n/a n/a n/a 460 525 600 n/a n/a n/a nm design 1. ?design? designates a parameter that is quantified during the design verification activity. table 9. kai ? 16000 ? cxa (gen1) description symbol min. nom. max. units sample plan 1 temperature tested at ( c) notes peak quantum efficiency blue green red qe max 44 38 29 n/a n/a n/a % design 2 peak quantum efficiency wavelength blue green red qe n/a n/a n/a 470 540 620 n/a n/a n/a nm design 2 1. ?design? designates a parameter that is quantified during the design verification activity. 2. this color filter set configuration (gen1) is not recommended for new designs. note: n/a = not applicable
kai ? 16000 www.onsemi.com 7 typical performance curves monochrome with microlens quantum efficiency figure 4. monochrome with microlens quantum efficiency 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 300 400 500 600 700 800 900 1000 1100 absolute quantum efficiency wavelength (nm) measured with ar coated cover glass monochrome without microlens quantum efficiency figure 5. monochrome without microlens quantum efficiency 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 300 400 500 600 700 800 900 1000 1100 absolute quantum efficiency wavelength (nm) measured without ar coated cover glass
kai ? 16000 www.onsemi.com 8 color with microlens quantum efficiency figure 6. color with microlens quantum efficiency
kai ? 16000 www.onsemi.com 9 angular quantum efficiency for the curves marked ?horizontal?, the incident light angle is varied in a plane parallel to the hccd. for the curves marked ?vertical?, the incident light angle is varied in a plane parallel to the vccd. monochrome with microlens figure 7. monochrome with microlens angular quantum efficiency 0 10 20 30 40 50 60 70 80 90 100 ? 30 ? 20 ? 10 0 10 20 30 relative quantum efficiency (%) angle (degress) vertical horizontal
kai ? 16000 www.onsemi.com 10 defect definitions operational conditions all defect tests performed at t int = t frame = 908 msec table 10. specifications description definition class x monochrome with microlens only class 1 class 2 monochrome class 2 color notes major dark field defective bright pixel defect 245 mv 150 150 300 300 2 major bright field defective dark pixel defect 15% minor dark field defective bright pixel defect 126 mv 1500 1500 3000 3000 3 cluster defect a group of 2 to ?n? contiguous major defective pixels, but no more than ?w? adjacent defects horizontally. 0 30 n = 20 w = 4 30 n = 20 w = 4 30 n = 20 w = 4 1, 2 column defect a group of more than 10 contiguous major defective pixels along a single column 0 0 4 15 1, 2 1. column and cluster defects are separated by no less than two (2) pixels in any direction (excluding single pixel defects). 2. tested at 27 c and 40 c. 3. tested at 40 c. note: class x sensors are offered strictly ?as available?. on semiconductor cannot guarantee delivery dates. please call for ava ilability. defect map the defect map supplied with each sensor is based upon testing at an ambient (27 c) temperature. minor point defects are not included in the defect map. all defective pixels are reference to pixel 1, 1 in the defect maps.
kai ? 16000 www.onsemi.com 11 test definitions test regions of interest image area roi: pixel (1, 1) to pixel (4872, 3248) only the active pixels are used for performance and defect tests. overclocking the test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. see figure 8 for a pictorial representation of the regions. figure 8. overclock regions of interest pixel 1,1 vertical overclock horizontal overclock h v
kai ? 16000 www.onsemi.com 12 tests global non ? uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 630 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 900 mv. global non ? uniformity is defined as globalnon ? uniformity 100 activeareastandarddeviation activeareasignal units: %rms. active area signal = active area average ? dark column average dark field defect test this test is performed under dark field conditions. the sensor is partitioned into 384 sub regions of interest, each of which is 203 by 203 pixels in size. in each region of interest, the median value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the ?defect definitions? section. bright field defect test this test is performed with the imager illuminated to a level such that the output is at approximately 630 mv. prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 900 mv. the average signal level of all active pixels is found. the bright and dark thresholds are set as: dark defect threshold = active area signal * threshold bright defect threshold = active area signal * threshold the sensor is then partitioned into 384 sub regions of interest, each of which is 203 by 203 pixels in size. in each region of interest, the average value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. example for major bright field defective pixels: ? average value of all active pixels is found to be 630 mv ? dark defect threshold: 630 mv * 15% = 95 mv ? bright defect threshold: 630 mv * 15% = 95 mv ? region of interest #1 selected. this region of interest is pixels 1, 1 to pixels 203, 203. ? median of this region of interest is found to be 630 mv. ? any pixel in this region of interest that is (630 + 95 mv) 725 mv in intensity will be marked defective. ? any pixel in this region of interest that is (630 ? 95 mv) 535 mv in intensity will be marked defective. ? all remaining 384 sub regions of interest are analyzed for defective pixels in the same manner.
kai ? 16000 www.onsemi.com 13 operation table 11. absolute maximum ratings description symbol minimum maximum units notes operating temperature t op ? 50 70 c 1 humidity rh 5 90 % 2 output bias current i out 0.0 ? 40 ma 3 off ? chip load c l 10 pf stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. noise performance will degrade at higher temperatures. 2. t = 25 c. excessive humidity will degrade mttf. 3. total for all outputs. maximum current is ? 20 ma for each output. avoid shorting output pins to ground or any low impedance source during operation. amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity). operat ion at these values will reduce mttf. table 12. maximum voltage ratings between pins description minimum maximum units notes rl, rr, h1sl, h1bl, h2sl, h2bl, h1sr, h1br, h2sr, h2br, hlastl, hlastr to esd 0 17 v pin to pin with esd protection ? 17 17 v 1 vddl, vddr to gnd 0 25 v 1. pins with esd protection are: rl, rr, h1sl, h1bl, h2sl, h2bl, h1sr, h1br, h2sr, h2sr, hlastl, and hlastr power ? up sequence 1. substrate 2. esd protection disable 3. all other clocks and biaeses table 13. dc bias operating conditions description symbol pins minimum nominal maximum units maximum dc current (ma) notes reset drain rd rdl, rdr +11.5 +12.0 +12.0 v output amplifier supply vdd vddl, vddr +14.5 +15.0 +15.5 v 4 ground gnd gnd 0.0 0.0 0.0 v substrate sub sub +8.0 vab +16.0 v 1, 5 esd protection disable esd esd ? 9.25 ? 9.0 ? 8.75 v 2 output bias current iout voutl, voutr ? 5.0 ? 10.0 ma 3 1. the operating of the substrate voltage, vab, will be marked on the shipping container for each device. the value of vab is se t such that the photodiode charge capacity is 30,000 electrons. 2. vesd must be at least 1 v more negative than h1_lo and h2_lo during sensor operation and during camera power turn on. 3. an output load sink must be applied to vout to activate output amplifier. 4. the maximum dc current is for one output unloaded. this is the maximum current that the first two stages of one output amplif ier will draw. this value is with vout disconnected. 5. refer to application note using interline ccd image sensors in high intensity visible lighting conditions
kai ? 16000 www.onsemi.com 14 ac operating conditions table 14. clock levels description pins symbol minimum nominal maximum units notes vertical ccd clock high v1, v3, v5, v7, v9, v11 v_2hi +8.5 +9.0 +9.5 v vertical ccd clocks midlevel v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12 v_1mid, v_2mid ? 0.2 0.0 +0.2 v vertical ccd clocks low v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12 v_1lo, v_2lo ? 9.5 ? 9.0 ? 8.5 v horizontal ccd clocks amplitude, phase 1 stor- age h1s h1sl, h1bl, h2sl, h2bl, h1sr, h1br, h2sr, h2brk h_amp +4.5 +5.0 +5.5 v horizontal ccd clocks low h1sl, h1bl, h2sl, h2bl, h1sr, h1br, h2sr, h2br h_lo ? 5.0 ? 4.5 ? 4.0 v horizontal last ccd amplitude hlastl, hlastr hlast_amp +4.5 +5.0 +5.5 v horizontal last ccd low hlastl, hlastr hlast_lo ? 5.0 ? 4.5 ? 4.0 v reset clock amplitude resetl, resetr r_amp +4.5 +5.0 +5.5 v reset clock low resetl, resetr r_lo ? 3.5 ? 3.0 ? 2.5 v electronic shutter voltage sub vshutter +44 +48 +52 v 1 fast dump high fdl, fdr fd_hi +4.5 +5.0 +5.5 v fast dump low fdl, fdr fd_lo ? 9.5 ? 9.0 ? 8.5 v 1. refer to application note using interline ccd image sensors in high intensity visible lighting conditions the figure below shows the dc bias (sub) and ac clock (vshutter) applied to the sub pin. both the dc bias and ac clock are referenced to ground. figure 9. sub vshutter gnd gnd
kai ? 16000 www.onsemi.com 15 table 15. clock line capacitances clocks capacitance units notes vertical ccd phase 1 to gnd 108 nf 1, 3 vertical ccd phase 2 to gnd 118 nf 1, 4 vertical ccd phase 1 to vertical ccd phase 2 56 nf 3, 4 h1s to gnd 27 pf 2 h2s to gnd 27 pf 2 h1b to gnd 13 pf 2 h2b to gnd 4 pf 2 h1s to h2b and h2s 13 pf 2 h1b to h2b and h2s 13 pf 2 h2s to h1b and h1s 13 pf 2 h2b to h1b and h1s 13 pf 2 hlast to gnd 20 pf 2 reset to gnd 10 pf fd to gnd 20 pf 1. gate capacitance to gnd is voltage dependent. value is for nominal vccd clock voltages. 2. for nominal hccd clock voltages, these values are for half of the imager (h1sl, h1bl, h2sl, h2bl and h1binl or h1sr, h1br, h2 sr, h2br and h1binr). 3. vertical ccd phase 1: v2, v4, v6, v8, v10, v12 4. vertical ccd phase 2: v1, v3, v5, v7, v9, v11
kai ? 16000 www.onsemi.com 16 timing table 16. requirements and characteristics description symbol minimum nominal maximum units notes vccd to hccd delay t hd 4 6 s vccd transfer time t vccd 4 6 s hccd to vccd delay t hl 50 ns photodiode transfer time t v3rd 10 12 s vccd pedestal time t 3p 200 600 s vccd delay t 3d 12 20 s vccd delay before pedestal t del 50 ns vccd delay before 1 st line t d1l 10 60 s reset pulse time t r 3.25 s vccd to hccd delay ? shutter t hds 6 s shutter pulse time t s 4 s shutter pulse delay t sd 1.5 s hccd clock period t h 33.3 ns vccd rise/fall time t vr 0.2 s fast dump gate leading delay t fdl 0.5 s fast dump gate trailing delay t fdt 0.5 s vccd line clock leading edge delay t vl 0.2 0.3 0.4 s vccd line clock trailing edge delay t vt 0.0 0.2 0.4 s main timing ? continuous mode figure 10. main timing ? continuous mode repeat for 3324 lines line timing vertical frame timing
kai ? 16000 www.onsemi.com 17 frame timing ? continuous mode figure 11. framing timing v1, v3, v5, v7, v9, v11 v2, v4, v6, v8, v10, v12 h1sl, h1bl, h1sr, h2br h2sl, h2bl, h2sr, h1br hlastl, hlastr v_2lo v_2mid v_1lo v_1mid v_2hi t 3p t 3d t d1l t del t v3rd h_lo h_lo h_amp h_amp hlast_lo hlast_amp
kai ? 16000 www.onsemi.com 18 line timing continuous mode line timing single output figure 12. line timing single output t vccd t l t hd r 2 1 pixel count 39 11 12 13 14 40 41 42 43 4941 4942 4943 4945 4946 4971 4972 44 4944 4970 v2, v4, v6, v8, v10, v12 v1, v3, v5, v7, v9, v11 h1sl, h1bl, h1sr, h2br h2sl, h2bl, h2sr, h1br hlastl, hlastr line timing double output figure 13. line timing dual output 2483 2484 2485 2487 2488 2491 2492 2486 2490 2489 t vccd t l t hd r 2 1 pixel count 39 11 12 13 14 40 41 42 43 44 v2, v4, v6, v8, v10, v12 v1, v3, v5, v7, v9, v11 h1sl, h1bl, h1sr, h1br h2sl, h2bl, h2sr, h2br hlastl, hlastr
kai ? 16000 www.onsemi.com 19 line timing detail single output figure 14. line timing detail single output t vccd t hd t hl v2, v4, v6, v8, v10, v12 v1, v3, v5, v7, v9, v11 h1sl, h1bl, h1sr, h2br h2sl, h2bl, h2sr, h1br hlastl, hlastr h_lo h_lo h_amp h_amp hlast_lo hlast_am p v_2lo v_2mid v_1lo v_1mid line timing detail edge alignment figure 15. line timing detail edge alignment low 0% 10% high 100% 90% 50% v1, v3, v5, v7, v9, v11 v2, v4, v6, v8, v10, v12 t vl t vt
kai ? 16000 www.onsemi.com 20 pixel timing figure 16. pixel timing hlast_lo hlast_amp h_lo h_amp h_lo h_amp r_lo r_amp h1sl, h1bl, h1sr, h2br h2sl, h2bl, h2sr, h1br hlastl, hlastr rr, rl t r
kai ? 16000 www.onsemi.com 21 fast line dump timing figure 17. fast line dump timing h1sl, h1bl, h1sr, h2br v2, v4, v6, v8, v10, v12 v1, v3, v5, v7, v9, v11 fdr, fdl fd_lo fd_hi t vccd t fdl t fdt t hd t vccd t vccd
kai ? 16000 www.onsemi.com 22 electronic shutter timing figure 18. electronic shutter timing h1sl, h1bl, h1sr, h2br h2sl, h2bl, h2sr, h1br hlastl, hlastr v2, v4, v6, v8, v10, v12 v1, v3, v5, v7, v9, v11 sub gnd vsub ves t hds t sd t s electronic shutter integration time definition figure 19. integration time definition integration time vshutter vsub v1, v3, v5, v7, v9, v11
kai ? 16000 www.onsemi.com 23 storage and handling table 17. storage conditions description symbol minimum maximum units notes temperature t ? 55 80 c 1 humidity rh 5 90 % 2 1. long ? term exposure toward the maximum temperature will accelerate color filter degradation. 2. t = 25 c. excessive humidity will degrade mttf. for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for information on soldering recommendations, please download the soldering and mounting techniques reference manual (solderrm/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com .
kai ? 16000 www.onsemi.com 24 mechanical drawings completed assembly figure 20. completed assembly (1 of 2)
kai ? 16000 www.onsemi.com 25 figure 21. completed assembly (2 of 2)
kai ? 16000 www.onsemi.com 26 cover glass figure 22. glass drawing notes: 1. multi ? layer anti ? reflective coating on 2 sides: double sided reflectance: range (nm) 420 ? 450 nm < 2% 450 ? 630 nm < 1% 630 ? 680 nm < 2% 2. dust, scratch specification ? 20 microns max 3. substrate ? schott d263t eco or equivalent 4. epoxy: nco ? 150hb thickness: 0.002? ? 0.005? coat both sides chamfer 0.008" [0.20] (typ. 8 plcs.) epoxy: nc0-150 hb thk. 0.002" - 0.005" chamfer 0.020" [0.50] (typ. 4 plcs.) 0.020r [0.50] (typ. 8 plcs.) ref. ar coat area
kai ? 16000 www.onsemi.com 27 glass transmission figure 23. cover glass transmission on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warrant y, representation or guarantee regarding the suitability of it s products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 kai ? 16000/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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